As described in "Design of CMOS Ultra LSI" by Takuo SUGANO, Baifukan, pp. 168 to 169, conventional methods of writing programs in a mask ROM include a diffusion layer programming method, an ion implantation programming method, a contact hole programming method, and the like. The mask ROM is divided into a NAND type and an OR type depending upon the layout of memory cells. Generally, a NAND type ROM can reduce the size of memory cell array more than a NOR type ROM, and the diffusion layer programming method and ion implantation programming method for a mask ROM can reduce the size of memory cell array more than the contact hole programming method.
FIG. 3 is a circuit diagram of a conventional NAND type ROM using the ion implantation programming method. In this circuit of the NAND type ROM, the direction of the channel of a MOS transistor 72 constituting a memory cell is aligned in the direction of a bit line 54. In an ordinary case, the threshold voltage (hereinafter abbreviated as Vth) of each MOS transistor 72 is set to a value corresponding to the enhancement type, and only the selected MOS transistors 72 are changed to have a value of Vth corresponding to the depletion type, to thereby write a desired program. In FIG. 3, reference numeral 62 represents a row decoder, and reference numeral 64 represents a column decoder. Transistors 42 are turned on during the memory read standby state to ground and discharge all word lines. Mask ROMs of this kind are disclosed, for example, in JP-A-62-195,786.
In reading data from a memory cell, first all the word lines 52 are set to an "H" level. Thereafter, the selected word line 52 is set to an "L" level and the selected bit line 54 is set to the "H" level. If Vth of the selected memory cell corresponds to the depletion type, a current flowing through the selected bit line 54 continues to flow even if the word line 52 is set to the "L" level. On the other hand, if the Vth corresponds to the enhancement type, a current flowing through the selected bit line 54 is cut off. In this manner, data in the memory cell can be read.
FIG. 4 is a circuit diagram of a conventional NOR type ROM using the ion implantation programming method. In this circuit of the NOR type ROM, a bit line 56, a MOS transistor 72, and a bit line 58 are repetitively disposed in this order in the row direction. The drain and source of each of the MOS transistor 72 disposed in the column direction are connected to the bit lines 56 and 58. The gates of the MOS transistors 72 disposed in the row direction are connected in common to a word line 52. All the bit lines 56 are electrically grounded, and the bit lines 58 are used for selecting a desired column.
In this circuit, Vth of each MOS transistor 72 is set to a value corresponding to the enhancement type allowing the MOS transistor to turn on when the word line 52 takes the "H" level. Only the selected memory cells are changed to have a value of Vth not allowing the memory cells to turn on when the word line 52 takes the "H" level. In this manner, a desired program is written in the mask ROM. In reading data from a memory cell, first all the word lines 52 are set to the "L" level or made open and all the bit lines are also made open. Thereafter, only the selected word line 52 is set to the "H" level and a pair of bit lines 56 and 58 connected to the memory cell are selected. If Vth of the selected memory cell has a value not allowing the memory cell to turn on when the word line 52 takes the "H" level, then the bit line 56 is grounded and the other bit line 58 is connected via a select transistor 74 to an operational amplifier 66. Data is read by checking the electrical conductivity of each selected memory cell as described above.
In the case of a NAND type ROM, as the number of memory cells disposed in a column direction increases, the total on-resistance of the cell transistors becomes larger, resulting in a smaller current flowing through the bit line and a slower access speed. For this reason, the number of memory cells in a column direction is limited.
In the case of a NOR type ROM, although it is free from the above disadvantages of the NAND type ROM, two bit lines are required for the memory cells in each column so that the structure of a decoder system becomes complicated. Therefore, the area of a memory cell array of a NOR type ROM becomes larger than that of a NAND type ROM.